From c9059fc7d0395e895520dc37019486339b43e3c9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sat, 15 Sep 2018 15:16:21 -0700
Subject: [PATCH] [ice40] TimingPortClass of LC.O ports without any inputs now
 TMG_IGNORE

---
 ice40/arch.cc | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 3983a24e..28d20adb 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -866,15 +866,22 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
             return TMG_COMB_INPUT;
         if (port == id_COUT || port == id_LO)
             return TMG_COMB_OUTPUT;
-        if (cell->lcInfo.dffEnable) {
-            clockPort = id_CLK;
-            if (port == id_O)
+        if (port == id_O) {
+            // LCs with no inputs are constant drivers
+            if (cell->lcInfo.inputCount == 0)
+                return TMG_IGNORE;
+            if (cell->lcInfo.dffEnable) {
+                clockPort = id_CLK;
                 return TMG_REGISTER_OUTPUT;
+            }
             else
-                return TMG_REGISTER_INPUT;
-        } else {
-            if (port == id_O)
                 return TMG_COMB_OUTPUT;
+        }
+        else {
+            if (cell->lcInfo.dffEnable) {
+                clockPort = id_CLK;
+                return TMG_REGISTER_INPUT;
+            }
             else
                 return TMG_COMB_INPUT;
         }