From cb9f3117babedcd04fa7a7cb885a7863e0af2316 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Miguel=20S=C3=A1nchez=20Garc=C3=ADa?=
 <soy.jmi2k@gmail.com>
Date: Tue, 1 Jul 2025 19:39:25 +0200
Subject: [PATCH] himbaechel: gatemate: replace VLA with C++ features (#1513)

---
 himbaechel/uarch/gatemate/bitstream.cc     | 2 +-
 himbaechel/uarch/gatemate/pack_clocking.cc | 2 +-
 himbaechel/uarch/gatemate/pack_io.cc       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/himbaechel/uarch/gatemate/bitstream.cc b/himbaechel/uarch/gatemate/bitstream.cc
index d258ae90..6a51c811 100644
--- a/himbaechel/uarch/gatemate/bitstream.cc
+++ b/himbaechel/uarch/gatemate/bitstream.cc
@@ -223,7 +223,7 @@ struct BitstreamBackend
     {
         ChipConfig cc;
         cc.chip_name = device;
-        int bank[uarch->dies][9] = {0};
+        std::vector<std::array<int, 9>> bank(uarch->dies);
         for (auto &cell : ctx->cells) {
             CfgLoc loc = get_config_loc(cell.second.get()->bel.tile);
             auto &params = cell.second.get()->params;
diff --git a/himbaechel/uarch/gatemate/pack_clocking.cc b/himbaechel/uarch/gatemate/pack_clocking.cc
index 7d840b3f..a21d463d 100644
--- a/himbaechel/uarch/gatemate/pack_clocking.cc
+++ b/himbaechel/uarch/gatemate/pack_clocking.cc
@@ -329,7 +329,7 @@ void GateMatePacker::remove_clocking()
 
 void GateMatePacker::pack_pll()
 {
-    int pll_index[uarch->dies] = {0};
+    std::vector<int> pll_index(uarch->dies);
     log_info("Packing PLLss..\n");
     for (auto &cell : ctx->cells) {
         CellInfo &ci = *cell.second;
diff --git a/himbaechel/uarch/gatemate/pack_io.cc b/himbaechel/uarch/gatemate/pack_io.cc
index dbf99840..1ff219b4 100644
--- a/himbaechel/uarch/gatemate/pack_io.cc
+++ b/himbaechel/uarch/gatemate/pack_io.cc
@@ -326,7 +326,7 @@ void GateMatePacker::pack_io_sel()
         cells.push_back(&ci);
     }
 
-    CellInfo *ddr[uarch->dies][9] = {nullptr}; // for each bank
+    std::vector<std::array<CellInfo *, 9>> ddr(uarch->dies); // for each bank
 
     auto set_out_clk = [&](CellInfo *cell, CellInfo *target) -> bool {
         NetInfo *clk_net = cell->getPort(id_CLK);