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Merge pull request #44 from YosysHQ/improve_timing_spec

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Speed up budget allocator using topographical ordering and update cell timing API
This commit is contained in:
David Shah
2018-08-08 19:23:47 +02:00
committed by GitHub
parent 2390f7f59c 751335977f
commit cd4e761bb7
10 changed files with 378 additions and 144 deletions
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8
ecp5/arch.cc
View File

@@ -375,7 +375,6 @@ BelId Arch::getPioByFunctionName(const std::string &name) const
}
std::vector<PortPin> Arch::getBelPins(BelId bel) const
{
std::vector<PortPin> ret;
NPNR_ASSERT(bel != BelId());
@@ -496,9 +495,10 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
return false;
}
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return IdString(); }
bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
{
return TMG_IGNORE;
}
std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
{

6
ecp5/arch.h
View File

@@ -828,10 +828,8 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false
// if no path exists
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
// Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock
bool isClockPort(const CellInfo *cell, IdString port) const;
// Get the port class, also setting clockPort if applicable
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const;
// Return true if a port is a net
bool isGlobalNet(const NetInfo *net) const;