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Add constant network test case.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman
2021-02-18 16:51:05 -08:00
parent 3e5a23ed5b
commit cf554f9338
5 changed files with 42 additions and 0 deletions
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8
fpga_interchange/examples/const_wire/Makefile Normal file
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DESIGN := wire
DESIGN_TOP := top
PACKAGE := csg324
include ../template.mk
build/wire.json: wire.v | build
yosys -c run.tcl

14
fpga_interchange/examples/const_wire/run.tcl Normal file
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yosys -import
read_verilog wire.v
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json build/wire.json

6
fpga_interchange/examples/const_wire/wire.v Normal file
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module top(output o, output o2);
assign o = 1'b0;
assign o2 = 1'b1;
endmodule

5
fpga_interchange/examples/const_wire/wire.xdc Normal file
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set_property PACKAGE_PIN N15 [get_ports o]
set_property PACKAGE_PIN N16 [get_ports o2]
set_property IOSTANDARD LVCMOS33 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports o2]