github.com/YosysHQ.nextpnr
1
0
Fork 0
mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-04-29 13:22:05 +00:00
Code Issues Releases Wiki Activity

archapi: Use arbitrary rather than actual placement in predictDelay

Browse Source 
This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.

A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
2021-12-19 16:41:34 +00:00
parent 56d5507333
commit ddb084e9a8
26 changed files with 89 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
common/arch_api.h
View File

@@ -110,7 +110,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual typename R::GroupPipsRangeT getGroupPips(GroupId group) const = 0;
virtual typename R::GroupGroupsRangeT getGroupGroups(GroupId group) const = 0;
// Delay Methods
virtual delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const = 0;
virtual delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const = 0;
virtual delay_t getDelayEpsilon() const = 0;
virtual delay_t getRipupDelayPenalty() const = 0;
virtual float getDelayNS(delay_t v) const = 0;

23
common/context.cc
View File

@@ -90,6 +90,25 @@ WireId Context::getNetinfoSinkWire(const NetInfo *net_info, const PortRef &sink,
return WireId();
}
delay_t Context::predictArcDelay(const NetInfo *net_info, const PortRef &sink) const
{
if (net_info->driver.cell == nullptr || net_info->driver.cell->bel == BelId() || sink.cell->bel == BelId())
return 0;
IdString driver_pin, sink_pin;
// Pick the first pin for a prediction; assume all will be similar enouhg
for (auto pin : getBelPinsForCellPin(net_info->driver.cell, net_info->driver.port)) {
driver_pin = pin;
break;
}
for (auto pin : getBelPinsForCellPin(sink.cell, sink.port)) {
sink_pin = pin;
break;
}
if (driver_pin == IdString() || sink_pin == IdString())
return 0;
return predictDelay(net_info->driver.cell->bel, driver_pin, sink.cell->bel, sink_pin);
}
delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &user_info) const
{
#ifdef ARCH_ECP5
@@ -98,7 +117,7 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
#endif
if (net_info->wires.empty())
return predictDelay(net_info, user_info);
return predictArcDelay(net_info, user_info);
WireId src_wire = getNetinfoSourceWire(net_info);
if (src_wire == WireId())
@@ -128,7 +147,7 @@ delay_t Context::getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &us
if (cursor == src_wire)
max_delay = std::max(max_delay, delay + getWireDelay(src_wire).maxDelay()); // routed
else
max_delay = std::max(max_delay, predictDelay(net_info, user_info)); // unrouted
max_delay = std::max(max_delay, predictArcDelay(net_info, user_info)); // unrouted
}
return max_delay;
}

2
common/context.h
View File

@@ -51,6 +51,8 @@ struct Context : Arch, DeterministicRNG
// --------------------------------------------------------------
delay_t predictArcDelay(const NetInfo *net_info, const PortRef &sink) const;
WireId getNetinfoSourceWire(const NetInfo *net_info) const;
SSOArray<WireId, 2> getNetinfoSinkWires(const NetInfo *net_info, const PortRef &sink) const;
size_t getNetinfoSinkWireCount(const NetInfo *net_info, const PortRef &sink) const;

2
common/nextpnr_namespaces.h
View File

@@ -33,6 +33,8 @@
#define USING_NEXTPNR_NAMESPACE
#endif
#define NPNR_UNUSED(x) ((void)x)
#if defined(__GNUC__) || defined(__clang__)
#define NPNR_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
#define NPNR_NORETURN __attribute__((noreturn))

2
common/place_common.cc
View File

@@ -50,7 +50,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (load_cell->bel == BelId())
continue;
if (timing_driven) {
delay_t net_delay = ctx->predictDelay(net, load);
delay_t net_delay = ctx->predictArcDelay(net, load);
auto slack = load.budget - net_delay;
if (slack < 0)
negative_slack += slack;

4
common/placer1.cc
View File

@@ -866,11 +866,11 @@ class SAPlacer
if (ctx->getPortTimingClass(net->driver.cell, net->driver.port, cc) == TMG_IGNORE)
return 0;
if (cfg.budgetBased) {
double delay = ctx->getDelayNS(ctx->predictDelay(net, net->users.at(user)));
double delay = ctx->getDelayNS(ctx->predictArcDelay(net, net->users.at(user)));
return std::min(10.0, std::exp(delay - ctx->getDelayNS(net->users.at(user).budget) / 10));
} else {
float crit = tmg.get_criticality(CellPortKey(net->users.at(user)));
double delay = ctx->getDelayNS(ctx->predictDelay(net, net->users.at(user)));
double delay = ctx->getDelayNS(ctx->predictArcDelay(net, net->users.at(user)));
return delay * std::pow(crit, crit_exp);
}
}

2
common/timing.cc
View File

@@ -1378,7 +1378,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
auto driver_wire = ctx->getNetinfoSourceWire(net);
auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
log_info(" prediction: %f ns estimate: %f ns\n",
ctx->getDelayNS(ctx->predictDelay(net, sink_ref)),
ctx->getDelayNS(ctx->predictArcDelay(net, sink_ref)),
ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
auto cursor = sink_wire;
delay_t delay;

8
common/timing_opt.cc
View File

@@ -99,7 +99,7 @@ class TimingOptimiser
continue;
for (auto user : net->users) {
if (user.cell == cell && user.port == port.first) {
if (ctx->predictDelay(net, user) >
if (ctx->predictArcDelay(net, user) >
1.1 * max_net_delay.at(std::make_pair(cell->name, port.first)))
return false;
}
@@ -111,7 +111,7 @@ class TimingOptimiser
BelId dstBel = user.cell->bel;
if (dstBel == BelId())
continue;
if (ctx->predictDelay(net, user) >
if (ctx->predictArcDelay(net, user) >
1.1 * max_net_delay.at(std::make_pair(user.cell->name, user.port))) {
return false;
@@ -413,7 +413,7 @@ class TimingOptimiser
for (size_t j = 0; j < pn->users.size(); j++) {
auto &usr = pn->users.at(j);
if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) {
original_delay += ctx->predictDelay(pn, usr);
original_delay += ctx->predictArcDelay(pn, usr);
break;
}
}
@@ -497,7 +497,7 @@ class TimingOptimiser
for (size_t j = 0; j < pn->users.size(); j++) {
auto &usr = pn->users.at(j);
if (usr.cell == path.at(i)->cell && usr.port == path.at(i)->port) {
total_delay += ctx->predictDelay(pn, usr);
total_delay += ctx->predictArcDelay(pn, usr);
break;
}
}