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Merge branch 'master' of github.com:YosysHQ/nextpnr into constids

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Clifford Wolf
2018-08-08 19:35:13 +02:00
parent a3ae3f9791 cd4e761bb7
commit f6189e4677
29 changed files with 1299 additions and 942 deletions
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10
docs/archapi.md
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@@ -431,13 +431,11 @@ Cell Delay Methods
Returns the delay for the specified path through a cell in the `&delay` argument. The method returns
false if there is no timing relationship from `fromPort` to `toPort`.
### IdString getPortClock(const CellInfo \*cell, IdString port) const
### TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
Returns the clock input port for the specified output port.
### bool isClockPort(const CellInfo \*cell, IdString port) const
Returns true if the specified port is a clock input.
Return the _timing port class_ of a port. This can be a register or combinational input or output; clock input or
output; general startpoint or endpoint; or a port ignored for timing purposes. For register ports, clockPort is set
to the associated clock port.
Placer Methods
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