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Code Issues Releases Wiki Activity
3,632 Commits 29 Branches 10 Tags
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Commit Graph

656 Commits

Author SHA1 Message Date
Miodrag Milanovic
afea345cc7 More pips added 2019-11-10 17:02:18 +01:00
Miodrag Milanovic
74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic
43c7b4fa21 Fixed V2, some more pips 2019-11-10 11:10:13 +01:00
Miodrag Milanovic
9a9265f4d2 more pips 2019-11-10 10:08:02 +01:00
Miodrag Milanovic
f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
David Shah
21c09c8b8f ecp5: Copy timing constraints across ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:27:51 +00:00
David Shah
58b7cb920f ecp5: Fix placement of ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:07:51 +00:00
David Shah
5cf0ed5ede ecp5: Allow setting drive strength for 3V3 IOs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 22:21:18 +01:00
David Shah
bac8335222 ecp5: Add constids for new timing cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:50:50 +01:00
David Shah
475fcd4425 ecp5: Add an error for out-of-sync constids and bba 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:38:28 +01:00
David Shah
36c07a0f45 ecp5: Fix routing to shared DSP control inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-25 09:37:13 +01:00
Miodrag Milanovic
49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic
d1feb2aa2d display horizontal wires, add some globals to list 2019-10-23 18:17:08 +02:00
David Shah
b582ba810c ecp5: Make database build depend on constids.inc 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:29:07 +01:00
Miodrag Milanovic
0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic
847910d986 type needs to be part of hash for GroupId 2019-10-20 10:03:37 +02:00
Miodrag Milanovic
e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
28d0313ccc Less types needed 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3da7af9f02 clk and lsr muxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
0b4ced96ec draw rest of slice wires and more from switchbox 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
3e117ce792 Optimize 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
49b12a828a Add other side of slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
1ae64d7bf5 Display rest of slice input wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
f7a6d4dc06 Start adding visible wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
eafc0e4e9e Added type to wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic
bfbb6dbf69 Draw swbox, smaller slices, proper io 2019-10-20 09:41:30 +02:00
David Shah
a22f86f861 ice40: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-19 13:01:00 +01:00
David Shah
cf5cbd1153 ecp5: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-18 15:58:57 +01:00
David Shah
8f86ccc412 ecp5: Add support for ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-11 14:52:31 +01:00
David Shah
f2fd1bf80a ecp5: Fix tristate IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:35:16 +01:00
David Shah
c6401413a4 ecp5: Add support for IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:23:35 +01:00
David Shah
a14555c8d1 ecp5: Add IDDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 12:07:56 +01:00
David Shah
21847a55e0 ecp5: Add ODDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 11:23:20 +01:00
David Shah
9b83e67460 ecp5: Preparations for new IO bels 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 10:55:10 +01:00
David Shah
cba36239a4 ecp5: Fix parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-04 14:54:31 +01:00
David Shah
d04e5954a6 ecp5: Adding support for 36-bit wide PDP RAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 12:01:33 +01:00
David Shah
cb71b488ec Merge pull request #332 from YosysHQ/dave/python-refactor 
Improving Python API and adding docs for it
 2019-09-19 20:15:42 +01:00
David Shah
8351ae275e Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-precompiled-bba 2019-09-19 16:02:10 +01:00