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nextpnr-0.1

nextpnr-0.2

nextpnr-0.3

nextpnr-0.4

nextpnr-0.5

nextpnr-0.6

nextpnr-0.7

nextpnr-0.8

nextpnr-0.9

Mono Color

• da8b5758cd Handle H00 and V00 Miodrag Milanovic 2019-11-11 13:30:11 +01:00
• 2827731210 More pips and fix for V01 Miodrag Milanovic 2019-11-11 12:49:26 +01:00
• 2898d8182d Fix typo David Shah 2019-11-11 09:44:11 +00:00
• 0cbc25f74a python: Add interactive.py for a REPL during PnR David Shah 2019-11-11 09:42:22 +00:00
• 522bbbc1f2 cleanup Miodrag Milanovic 2019-11-11 09:32:28 +01:00
• 6e349db55b proper h06 and v06 Miodrag Milanovic 2019-11-11 08:58:46 +01:00
• afea345cc7 More pips added Miodrag Milanovic 2019-11-10 17:02:18 +01:00
• 74f2c4a73b more pips, and valid mapping Miodrag Milanovic 2019-11-10 15:24:06 +01:00
• 43c7b4fa21 Fixed V2, some more pips Miodrag Milanovic 2019-11-10 11:10:13 +01:00
• 9a9265f4d2 more pips Miodrag Milanovic 2019-11-10 10:08:02 +01:00
• f6d74cb7a9 Draw some pips, fixed H6 and V6 Miodrag Milanovic 2019-11-09 13:12:20 +01:00
• 6a335411da Merge pull request #350 from pepijndevos/newslice David Shah 2019-11-08 16:28:39 +00:00
• a4848f6902 more formatting Pepijn de Vos 2019-11-08 17:18:50 +01:00
• 5dd1e5e51e return FF_USED, formatting, correct INIT Pepijn de Vos 2019-11-08 17:15:12 +01:00
• 7c362f292c dedicated output for LUT in GENERIC_SLICE Pepijn de Vos 2019-11-08 15:54:27 +01:00
• caf7abdb8d cmake: Add boost system library David Shah 2019-11-06 13:51:05 +00:00
• 21c09c8b8f ecp5: Copy timing constraints across ECLKBRIDGECS David Shah 2019-11-01 16:27:51 +00:00
• 58b7cb920f ecp5: Fix placement of ECLKBRIDGECS David Shah 2019-11-01 16:02:23 +00:00
• 5cf0ed5ede ecp5: Allow setting drive strength for 3V3 IOs David Shah 2019-10-26 22:21:18 +01:00
• bac8335222 ecp5: Add constids for new timing cell types David Shah 2019-10-26 20:50:50 +01:00
• 475fcd4425 ecp5: Add an error for out-of-sync constids and bba David Shah 2019-10-26 20:38:28 +01:00
• 371d33146f Merge branch 'master' of ssh.github.com:YosysHQ/nextpnr David Shah 2019-10-25 09:37:20 +01:00
• 36c07a0f45 ecp5: Fix routing to shared DSP control inputs David Shah 2019-10-25 09:37:13 +01:00
• 49760a9ea8 Show V02/V06/H02/H06 Miodrag Milanovic 2019-10-25 09:28:08 +02:00
• ae1e7837bb Merge pull request #346 from xobs/fix-ice40-pregenerated-bba David Shah 2019-10-25 07:55:35 +01:00
• f2b9cc6d23 sdf: Working on support for CVC David Shah 2019-10-24 12:37:07 +01:00
• 8343488bdf sdf: Improve SDF output David Shah 2019-10-24 10:43:18 +01:00
• 5b99382002 ice40: cmake: fix build with pregenerated bba path Sean Cross 2019-10-24 13:35:38 +08:00
• d1feb2aa2d display horizontal wires, add some globals to list Miodrag Milanovic 2019-10-23 18:17:08 +02:00
• b582ba810c ecp5: Make database build depend on constids.inc David Shah 2019-10-20 10:29:07 +01:00
• 0d2ae5cc9d Split graphics calls for wires into gfx.cc Miodrag Milanovic 2019-10-20 11:12:26 +02:00
• 847910d986 type needs to be part of hash for GroupId Miodrag Milanovic 2019-10-20 10:03:37 +02:00
• e9ae0cf7ce muxes only together with slices Miodrag Milanovic 2019-10-20 09:38:08 +02:00
• eaf760768b Remove not used line Miodrag Milanovic 2019-10-20 09:34:32 +02:00
• e69bb4c077 Simplify layout of elements Miodrag Milanovic 2019-10-20 09:34:02 +02:00
• 3b01d2fbce fix slice wire Miodrag Milanovic 2019-10-18 15:10:19 +02:00
• 399a137a77 bound signals Miodrag Milanovic 2019-10-12 19:44:18 +02:00
• 8c79044d43 more wires between switchboxes Miodrag Milanovic 2019-10-12 19:07:54 +02:00
• 4cbdc388b8 Add more types of wires Miodrag Milanovic 2019-10-12 17:53:46 +02:00
• 28d0313ccc Less types needed Miodrag Milanovic 2019-10-12 15:26:24 +02:00
• 966d0dec19 finixed slice wires Miodrag Milanovic 2019-10-12 13:56:13 +02:00
• 74da9cc424 wd wires Miodrag Milanovic 2019-10-12 13:47:01 +02:00
• 4b79050ef4 Fix look of some wires Miodrag Milanovic 2019-10-12 12:19:44 +02:00
• a59faa8df0 Add output wires Miodrag Milanovic 2019-10-12 12:06:17 +02:00
• 07a8022a1f fix mux display Miodrag Milanovic 2019-10-12 10:47:37 +02:00
• a11cc8791b set wire active flag Miodrag Milanovic 2019-10-12 10:35:52 +02:00
• 3da7af9f02 clk and lsr muxes Miodrag Milanovic 2019-10-12 09:27:55 +02:00
• 0b4ced96ec draw rest of slice wires and more from switchbox Miodrag Milanovic 2019-10-11 17:52:57 +02:00
• 3e117ce792 Optimize Miodrag Milanovic 2019-10-11 16:26:08 +02:00
• 49b12a828a Add other side of slice wires Miodrag Milanovic 2019-10-11 15:31:07 +02:00
• 1ae64d7bf5 Display rest of slice input wires Miodrag Milanovic 2019-10-11 08:15:02 +02:00
• d1dc2c3a5f Add more zoom Miodrag Milanovic 2019-10-06 18:09:23 +02:00
• f7a6d4dc06 Start adding visible wires Miodrag Milanovic 2019-10-06 17:59:44 +02:00
• eafc0e4e9e Added type to wire Miodrag Milanovic 2019-10-06 16:24:43 +02:00
• bfbb6dbf69 Draw swbox, smaller slices, proper io Miodrag Milanovic 2019-10-06 11:26:56 +02:00
• 4775930e49 sdf: Add basic support for writing SDF files David Shah 2019-10-19 16:52:47 +01:00
• c0484a317d sdf: Framework for writing out SDF files David Shah 2019-10-19 16:08:11 +01:00
• a22f86f861 ice40: Preserve top level IO properly David Shah 2019-10-18 16:32:55 +01:00
• cf5cbd1153 ecp5: Preserve top level IO properly David Shah 2019-10-18 15:58:57 +01:00
• 872e296f7b Merge pull request #342 from xobs/msvc-static-fix David Shah 2019-10-18 12:09:40 +01:00
• 0db8995e81 cmake: don't link libutil on windows Sean Cross 2019-10-18 16:19:30 +08:00
• c365dd1cab Merge pull request #341 from YosysHQ/dave/ice40-pcf-frequency David Shah 2019-10-13 20:18:46 +01:00
• 8c0610e84f ice40: Add set_frequency pcf command; and document pcf David Shah 2019-10-13 18:48:39 +01:00
• ee769420e3 Merge pull request #340 from YosysHQ/dave/ecp5_io David Shah 2019-10-13 11:17:23 +01:00
• 8f86ccc412 ecp5: Add support for ECLKBRIDGECS David Shah 2019-10-11 14:52:31 +01:00
• 58db38c746 Merge pull request #338 from YosysHQ/docs David Shah 2019-10-11 10:02:38 +01:00
• f2fd1bf80a ecp5: Fix tristate IO registers David Shah 2019-10-09 14:35:16 +01:00
• c6401413a4 ecp5: Add support for IO registers David Shah 2019-10-09 14:23:35 +01:00
• a14555c8d1 ecp5: Add IDDR71B support David Shah 2019-10-09 12:07:56 +01:00
• 21847a55e0 ecp5: Add ODDR71B support David Shah 2019-10-09 11:23:20 +01:00
• 9b83e67460 ecp5: Preparations for new IO bels David Shah 2019-10-09 10:55:10 +01:00
• cc8eaf7206 Merge pull request #339 from YosysHQ/dave/cmakefix Miodrag Milanović 2019-10-09 11:54:06 +02:00
• e9cced57bf Apply Boost CMake fix to all OSs David Shah 2019-10-09 10:46:18 +01:00
• cba36239a4 ecp5: Fix parameters David Shah 2019-10-04 14:54:31 +01:00
• a00d6c75aa docs: Improvements to coding notes David Shah 2019-10-03 11:34:31 +01:00
• 2c59ce9df5 Merge pull request #337 from YosysHQ/dave/ecp5_pdp16 David Shah 2019-10-03 09:52:23 +01:00
• d04e5954a6 ecp5: Adding support for 36-bit wide PDP RAMs David Shah 2019-10-01 10:36:22 +01:00
• cb8d90bcbf clangformat David Shah 2019-10-01 12:01:24 +01:00
• 137d9d33c1 docs: Working on coding tips David Shah 2019-09-29 15:50:08 +02:00
• 72244066bb docs: More netlist documentation David Shah 2019-09-29 15:22:56 +02:00
• cfe86dfd15 docs: Add docs for CellInfo and NetInfo David Shah 2019-09-29 12:12:28 +02:00
• 7cd1e04951 Fix issue with latest boost on macOS, fixes #322 Miodrag Milanovic 2019-09-28 12:33:45 +02:00
• 30e3c8469b ice40: Add support for PLL DELAY_ADJUSTMENT_MODE David Shah 2019-09-23 19:46:31 +01:00
• 395db49b21 Merge pull request #335 from YosysHQ/dave/fix-334 David Shah 2019-09-23 16:30:58 +01:00
• fac998ddcb ice40: Fix carry feed-out when we have to split the chain next David Shah 2019-09-23 15:51:05 +01:00
• cb71b488ec Merge pull request #332 from YosysHQ/dave/python-refactor David Shah 2019-09-19 20:15:42 +01:00
• f8b3c13a53 Merge pull request #331 from xobs/precompiled-bba David Shah 2019-09-19 20:15:12 +01:00
• 8351ae275e Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-precompiled-bba David Shah 2019-09-19 16:02:10 +01:00
• f8719a5717 Merge pull request #330 from zeldin/bba David Shah 2019-09-19 15:57:23 +01:00
• 6bb098b476 docs: Add Python API documentation David Shah 2019-09-19 15:49:49 +01:00
• 7cda79f9b7 README: document PREGENERATED_BBA_PATH Sean Cross 2019-09-17 11:33:39 +08:00
• 96130efc34 ice40: support PREGENERATED_BBA_PATH Sean Cross 2019-09-17 11:33:17 +08:00
• 062091e9e4 ecp5: add support for PREGENERATED_BBA_PATH Sean Cross 2019-09-17 11:32:44 +08:00
• 5cd2b55f1f python: Adding helper functions for netlist modification David Shah 2019-09-15 19:30:56 +01:00
• d5e4986e1b python: Refactor out bindings shared between ECP5 and iCE40 David Shah 2019-09-15 16:15:07 +01:00
• c2299c8972 python: Fix getWireBelPins David Shah 2019-09-15 15:59:16 +01:00
• 2f9b04fd56 CMake: Generate chipdbs in build tree when building out-of-tree Marcus Comstedt 2019-09-15 13:27:41 +02:00
• 3d9ce8836c bba: Require explicit endianness flag, and supply it Marcus Comstedt 2019-09-15 12:30:03 +02:00
• dd40c41ffc bba: Default to native endian in bbasm Marcus Comstedt 2019-09-15 09:42:52 +02:00
• bc6b47efe0 Merge pull request #329 from YosysHQ/dave/net_aliases David Shah 2019-09-13 19:01:26 +01:00