Clifford Wolf 032c94d094 Add blinky post-synthesis testbench ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2018-06-10 14:31:38 +02:00

..

.gitignore

Add blinky post-synthesis testbench

2018-06-10 14:31:38 +02:00

bitstream.cc

ice40: Set config bits for unused IO

2018-06-10 13:38:34 +02:00

bitstream.h

ice40: Write logic cell config to bitstream

2018-06-10 12:58:05 +02:00

blinky_map.v

ice40: Fix techmap

2018-06-10 13:33:47 +02:00

blinky_tb.v

Add blinky post-synthesis testbench

2018-06-10 14:31:38 +02:00

blinky.sh

Add blinky post-synthesis testbench

2018-06-10 14:31:38 +02:00

blinky.v

Renamed LOC attribute to BEL, fix ice40 IO bel names

2018-06-09 19:52:22 +02:00

blinky.ys

Add iCE40 blinky example

2018-05-31 18:10:36 +02:00

chip.cc

Fix ice40 pip/switch locked performance issue

2018-06-10 14:08:00 +02:00

chip.h

Fix ice40 pip/switch locked performance issue

2018-06-10 14:08:00 +02:00

chipdb.py

Fix ice40 pip/switch locked performance issue

2018-06-10 14:08:00 +02:00

family.cmake

cmake: Add HX1K-only builds support

2018-06-07 13:20:16 +02:00

main.cc

ice40: Write logic cell config to bitstream

2018-06-10 12:58:05 +02:00

portpins.inc

Add very basic router

2018-06-09 18:19:20 +02:00

pybindings.cc

Getting rid of .nil() methods, compare with zero- and default-constructed objects instead

2018-06-09 18:41:38 +02:00