Clifford Wolf 78f40ca0af Change DelayInfo semantics to what we actually need ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2018-07-21 13:52:59 +02:00

..

synth

ecp5: Tidying up examples

2018-07-18 16:31:55 +02:00

.gitignore

ecp5: Adding complete binary blob writer to Trellis importer

2018-07-11 10:41:36 +02:00

arch_place.cc

ecp5: Adding a slow and conservative placement validity checker

2018-07-17 16:18:06 +02:00

arch_pybindings.cc

ecp5: Implementing core arch.h functions

2018-07-11 10:41:36 +02:00

arch_pybindings.h

Revert "Move read methods to ReadMethods, remove some legacy access to Arch"

2018-07-14 18:50:23 +01:00

arch.cc

ecp5: Add support for pin name constraints using 'LOC' attributes

2018-07-18 16:01:53 +02:00

arch.h

Add getWireDelay API

2018-07-21 13:38:44 +02:00

archdefs.h

Change DelayInfo semantics to what we actually need

2018-07-21 13:52:59 +02:00

bitstream.cc

ecp5: Fixing packer bugs

2018-07-17 16:45:39 +02:00

bitstream.h

ecp5: Adding bitstream gen for pips and LUT init

2018-07-11 10:42:09 +02:00

cells.cc

ecp5: Simple packer working

2018-07-18 09:52:53 +02:00

cells.h

ecp5: LUT packer

2018-07-17 15:44:36 +02:00

family.cmake

ecp5: Build all chip types

2018-07-17 12:46:25 +02:00

main.cc

ecp5: Add support for pin name constraints using 'LOC' attributes

2018-07-18 16:01:53 +02:00

pack.cc

ecp5: Add support for pin name constraints using 'LOC' attributes

2018-07-18 16:01:53 +02:00

place_legaliser.cc

ecp5: Implementing (at least stubs) most of arch.cc

2018-07-11 10:41:36 +02:00

place_legaliser.h

ecp5: Implementing (at least stubs) most of arch.cc

2018-07-11 10:41:36 +02:00

portpins.inc

ecp5: Improving SLICE bel

2018-07-12 10:09:56 +02:00

trellis_import.py

ecp5: Adding PIO data to chipdb

2018-07-18 15:34:22 +02:00