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YosysHQ.nextpnr/ecp5
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David Shah 1c1c096861 ecp5: Fix 25k DDRDLLA bitstream gen 
Signed-off-by: David Shah <dave@ds0.me>
2019-11-29 10:56:04 +00:00
..
docs
ecp5: Add list of supported primitives
2019-02-24 10:28:25 +01:00
resource
Add missing files and missing includes for MSVC
2018-08-02 14:51:05 +02:00
.gitignore
ecp5: Adding complete binary blob writer to Trellis importer
2018-07-11 10:41:36 +02:00
arch_place.cc
ecp5: Fix routing to shared DSP control inputs
2019-10-25 09:37:13 +01:00
arch_pybindings.cc
python: Refactor out bindings shared between ECP5 and iCE40
2019-09-15 16:15:07 +01:00
arch_pybindings.h
python: Fix getWireBelPins
2019-09-15 15:59:16 +01:00
arch.cc
ecp5: Add an error for out-of-sync constids and bba
2019-10-26 20:38:28 +01:00
arch.h
ecp5: Fix 25k DDRDLLA bitstream gen
2019-11-29 10:56:04 +00:00
archdefs.h
ecp5: Add an error for out-of-sync constids and bba
2019-10-26 20:38:28 +01:00
baseconfigs.cc
ecp5: Embed baseconfig
2019-02-08 13:44:15 +00:00
bitstream.cc
ecp5: Fix 25k DDRDLLA bitstream gen
2019-11-29 10:56:04 +00:00
bitstream.h
ecp5: Remove libtrellis link for bitstream gen
2018-08-01 15:58:38 +02:00
cells.cc
ice40: Preserve top level IO properly
2019-10-19 13:01:00 +01:00
cells.h
ecp5: Add DELAYF/DELAYG support
2019-02-24 10:28:25 +01:00
config.cc
ecp5: Working on BRAM initialisation
2018-10-09 13:13:16 +01:00
config.h
ecp5: Working on BRAM initialisation
2018-10-09 13:13:16 +01:00
constids.inc
ecp5: Add constids for new timing cell types
2019-10-26 20:50:50 +01:00
dcu_bitstream.h
ecp5: New Property interface
2019-08-05 17:22:37 +01:00
family.cmake
ecp5: Make database build depend on constids.inc
2019-10-20 10:29:07 +01:00
gfx.h
ecp5: Add Bel graphics
2018-07-31 14:39:37 +02:00
globals.cc
Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr"
2019-11-20 17:10:11 +00:00
globals.h
ecp5: Separate global promotion and routing
2018-10-31 16:22:34 +00:00
iotypes.inc
ecp5: Helper functions for I/O placement and checking
2018-07-23 18:56:46 +02:00
lpf.cc
Use properties for settings and save in json
2019-06-12 18:34:34 +02:00
main.cc
Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr"
2019-11-20 17:10:11 +00:00
pack.cc
ecp5: Fix placement of DDRDLLA
2019-11-29 10:50:13 +00:00
pio.cc
Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with Windows-provided io.h.
2018-11-03 13:11:01 -04:00
pio.h
Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with Windows-provided io.h.
2018-11-03 13:11:01 -04:00
trellis_import.py
ecp5: Add constids for new timing cell types
2019-10-26 20:50:50 +01:00