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YosysHQ.nextpnr/mistral
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Lofty b81ba2d6c2 mistral: add getChipName 
Signed-off-by: Lofty <dan.ravensloft@gmail.com>
2021-05-15 22:50:56 +01:00
..
arch_pybindings.cc
msitral: Fix pip iterator Python bindings
2021-05-15 14:54:33 +01:00
arch_pybindings.h
mistral: Python and GUI stub
2021-05-15 14:54:33 +01:00
arch.cc
mistral: Add MISTRAL_CLKBUF cell type
2021-05-15 21:28:48 +01:00
arch.h
mistral: add getChipName
2021-05-15 22:50:56 +01:00
archdefs.cc
mistral: Add some packing logic based on nexus
2021-05-15 14:54:33 +01:00
archdefs.h
mistral: Tidying up
2021-05-15 14:54:33 +01:00
base_bitstream.cc
mistral: Tidying up
2021-05-15 14:54:33 +01:00
bitstream.cc
mistral: Add MISTRAL_CLKBUF cell type
2021-05-15 21:28:48 +01:00
constids.inc
mistral: Add MISTRAL_CLKBUF cell type
2021-05-15 21:28:48 +01:00
family.cmake
mistral: Setting some more boilerplate bits
2021-05-15 14:54:33 +01:00
globals.cc
mistral: Add MISTRAL_CLKBUF cell type
2021-05-15 21:28:48 +01:00
io.cc
mistral: Tidying up
2021-05-15 14:54:33 +01:00
lab.cc
mistral: Tidying up
2021-05-15 14:54:33 +01:00
main.cc
mistral: Add stub RBF generation
2021-05-15 14:54:33 +01:00
pack.cc
mistral: Tidying up
2021-05-15 14:54:33 +01:00
pins.cc
mistral: Tidying up
2021-05-15 14:54:33 +01:00
qsf.cc
mistral: Tidying up
2021-05-15 14:54:33 +01:00