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YosysHQ.nextpnr/mistral
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gatecat bacba274a2 mistral: Write LUT inits 
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-15 14:54:33 +01:00
..
arch_pybindings.cc
mistral: Python and GUI stub
2021-05-15 14:54:33 +01:00
arch_pybindings.h
mistral: Python and GUI stub
2021-05-15 14:54:33 +01:00
arch.cc
mistral: Implement some misc. things
2021-05-15 14:54:33 +01:00
arch.h
mistral: Add stub RBF generation
2021-05-15 14:54:33 +01:00
archdefs.cc
mistral: Add some packing logic based on nexus
2021-05-15 14:54:33 +01:00
archdefs.h
mistral: Add some packing logic based on nexus
2021-05-15 14:54:33 +01:00
base_bitstream.cc
mistral: Setting some more boilerplate bits
2021-05-15 14:54:33 +01:00
bitstream.cc
mistral: Write LUT inits
2021-05-15 14:54:33 +01:00
constids.inc
mistral: Rename clock buffer primitive
2021-05-15 14:54:33 +01:00
family.cmake
mistral: Setting some more boilerplate bits
2021-05-15 14:54:33 +01:00
globals.cc
mistral: Rename clock buffer primitive
2021-05-15 14:54:33 +01:00
io.cc
mistral: Add IO packing
2021-05-15 14:54:33 +01:00
lab.cc
mistral: Write LUT inits
2021-05-15 14:54:33 +01:00
main.cc
mistral: Add stub RBF generation
2021-05-15 14:54:33 +01:00
pack.cc
mistral: Add IO packing
2021-05-15 14:54:33 +01:00
pins.cc
mistral: Add the 'pin style' stuff based on Nexus
2021-05-15 14:54:33 +01:00
qsf.cc
mistral: Add IO packing
2021-05-15 14:54:33 +01:00