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YosysHQ.nextpnr/generic/examples
Josef Gajdusek 0a8a848a72 Minor UX improvements to the generic example code (#1706)
* generic: Fix Python path not including the examples/ directory in the example

It seems that at some point, the embedded Python stopped including the
directory that nextpnr-generic was executed in inside of its sys.path.
This likely happened by de3d5be8 specifying an explicit argv to
the interpreter init function.

* generic: Improve the example for K != 4

Configuring K < 4 used to result in "dangling" inputs to the cells being
generated (those are just not driven by anything in the resulting Verilog/JSON).

Configuring K > 4 used to result in an assertion crash in cells.cc.

The ctx.setLutK call fixes both cases.
2026-04-28 13:08:44 +02:00
..

Generic Architecture Example

This contains a simple, artificial, example of the nextpnr generic API.

  • simple.py procedurally generates a simple FPGA architecture with IO at the edges, logic slices in all other tiles, and interconnect only between adjacent tiles

  • simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing)

  • write_fasm.py uses the nextpnr Python API to write a FASM file for a design

  • bitstream.py uses write_fasm.py to create a FASM ("FPGA assembly") file for the place-and-routed design

  • Run simple.sh to build an example design on the FPGA above