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9 lines
142 B
Verilog
9 lines
142 B
Verilog
module top(input clk, output reg [7:0] leds);
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reg [25:0] ctr;
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always @(posedge clk)
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ctr <= ctr + 1'b1;
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assign leds = ctr[25:18];
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endmodule |