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11 lines
273 B
Verilog
11 lines
273 B
Verilog
module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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LUT #(.K(`LUT_K), .INIT(LUT)) _TECHMAP_REPLACE_ (.I(A), .Q(Y));
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endmodule
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module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
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