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17 lines
239 B
Verilog
17 lines
239 B
Verilog
module top(input rst, output reg [7:0] leds);
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wire clk;
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(* BEL="X1Y0/IO0" *) INBUF ib_i (.O(clk));
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reg [7:0] ctr;
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always @(posedge clk)
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if (rst)
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ctr <= 8'h00;
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else
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ctr <= ctr + 1'b1;
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assign leds = {4'b1010, ctr[7:4]};
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endmodule
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