David Shah d0bd657551 ice40: Write logic cell config to bitstream ...

Signed-off-by: David Shah <davey1576@gmail.com>

2018-06-10 12:58:05 +02:00

..

.gitignore

Fix race condition and optimise the build

2018-06-02 14:17:31 +02:00

bitstream.cc

ice40: Write logic cell config to bitstream

2018-06-10 12:58:05 +02:00

bitstream.h

ice40: Write logic cell config to bitstream

2018-06-10 12:58:05 +02:00

blinky_map.v

Add iCE40 blinky example

2018-05-31 18:10:36 +02:00

blinky.v

Renamed LOC attribute to BEL, fix ice40 IO bel names

2018-06-09 19:52:22 +02:00

blinky.ys

Add iCE40 blinky example

2018-05-31 18:10:36 +02:00

chip.cc

ice40: Lock out mutually exclusive pips

2018-06-10 12:17:55 +02:00

chip.h

ice40: Lock out mutually exclusive pips

2018-06-10 12:17:55 +02:00

chipdb.py

ice40: Adding non-routing config bits to database

2018-06-10 11:14:50 +02:00

family.cmake

cmake: Add HX1K-only builds support

2018-06-07 13:20:16 +02:00

main.cc

ice40: Write logic cell config to bitstream

2018-06-10 12:58:05 +02:00

portpins.inc

Add very basic router

2018-06-09 18:19:20 +02:00

pybindings.cc

Getting rid of .nil() methods, compare with zero- and default-constructed objects instead

2018-06-09 18:41:38 +02:00