mirror of
https://github.com/YosysHQ/nextpnr.git
synced 2026-01-11 23:53:21 +00:00
d6483adb4d
* Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
94 lines
3.0 KiB
CMake
94 lines
3.0 KiB
CMake
option(HIMBAECHEL_SPLIT "Whether to build one executable per Himbächel microarchitecture" OFF)
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set(HIMBAECHEL_SOURCES
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arch.cc
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archdefs.h
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arch.h
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arch_pybindings.cc
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arch_pybindings.h
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chipdb.h
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himbaechel_api.cc
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himbaechel_api.h
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himbaechel_constids.h
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himbaechel_gfxids.h
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himbaechel_helpers.cc
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himbaechel_helpers.h
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)
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if (HIMBAECHEL_SPLIT)
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function(add_nextpnr_himbaechel_microarchitecture microtarget)
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cmake_parse_arguments(arg "" "" "CORE_SOURCES;TEST_SOURCES" ${ARGN})
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list(TRANSFORM arg_CORE_SOURCES PREPEND ${CMAKE_CURRENT_SOURCE_DIR}/)
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list(TRANSFORM arg_TEST_SOURCES PREPEND ${CMAKE_CURRENT_SOURCE_DIR}/)
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add_nextpnr_architecture(himbaechel-${microtarget}
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CORE_SOURCES ${HIMBAECHEL_SOURCES}
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MAIN_SOURCE main.cc
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CURRENT_SOURCE_DIR ${CMAKE_SOURCE_DIR}/himbaechel
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CURRENT_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}
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)
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target_sources(nextpnr-himbaechel-${microtarget}-core INTERFACE ${arg_CORE_SOURCES})
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if (BUILD_TESTS)
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target_sources(nextpnr-himbaechel-${microtarget}-test PRIVATE ${arg_TEST_SOURCES})
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endif()
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endfunction()
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else()
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add_nextpnr_architecture(himbaechel
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CORE_SOURCES ${HIMBAECHEL_SOURCES}
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MAIN_SOURCE main.cc
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)
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function(add_nextpnr_himbaechel_microarchitecture microtarget)
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cmake_parse_arguments(arg "" "" "CORE_SOURCES;TEST_SOURCES" ${ARGN})
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target_sources(nextpnr-himbaechel-core INTERFACE ${arg_CORE_SOURCES})
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add_library(nextpnr-himbaechel-${microtarget}-bba INTERFACE EXCLUDE_FROM_ALL)
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add_dependencies(nextpnr-himbaechel-bba nextpnr-himbaechel-${microtarget}-bba)
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add_library(nextpnr-himbaechel-${microtarget}-chipdb INTERFACE EXCLUDE_FROM_ALL)
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target_link_libraries(nextpnr-himbaechel-core INTERFACE nextpnr-himbaechel-${microtarget}-chipdb)
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if (BUILD_TESTS)
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target_sources(nextpnr-himbaechel-test PRIVATE ${arg_TEST_SOURCES})
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endif()
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endfunction()
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endif()
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set(HIMBAECHEL_UARCHES example gowin xilinx ng-ultra gatemate)
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set(HIMBAECHEL_UARCH "" CACHE STRING "Microarchitectures for nextpnr-himbaechel build")
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set_property(CACHE HIMBAECHEL_UARCH PROPERTY STRINGS ${HIMBAECHEL_UARCHES})
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if (NOT HIMBAECHEL_UARCH)
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message(STATUS "Microarchitecture needs to be set, set desired one with -DHIMBAECHEL_UARCH=xxx")
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message(STATUS "Supported Himbächel microarchitectures are :")
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message(STATUS " all")
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foreach (item ${HIMBAECHEL_UARCHES})
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message(STATUS " ${item}")
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endforeach()
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message(FATAL_ERROR "Microarchitecture setting is mandatory")
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endif()
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if (HIMBAECHEL_UARCH STREQUAL "all")
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set(HIMBAECHEL_UARCH ${HIMBAECHEL_UARCHES})
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endif()
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foreach (uarch ${HIMBAECHEL_UARCH})
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if (NOT uarch IN_LIST HIMBAECHEL_UARCHES)
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message(FATAL_ERROR "Microarchitecture ${uarch} is not a supported Himbächel microarchitecture")
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endif()
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message(STATUS "Configuring Himbächel microarchitecture: ${uarch}")
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add_subdirectory(uarch/${uarch})
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endforeach()
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