mirror of
https://github.com/YosysHQ/nextpnr.git
synced 2026-01-11 23:53:21 +00:00
d6483adb4d
* Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
68 lines
2.0 KiB
CMake
68 lines
2.0 KiB
CMake
set(SOURCES
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bitstream.cc
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ccf.cc
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cells.cc
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config.cc
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config.h
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constids.inc
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extra_data.h
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gatemate.cc
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gatemate.h
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gfx.cc
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gfxids.inc
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pack.cc
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pack.h
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pll.cc
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)
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set(TEST_SOURCES
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tests/lut.cc
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tests/testing.cc
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tests/main.cc
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)
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add_nextpnr_himbaechel_microarchitecture(${uarch}
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CORE_SOURCES ${SOURCES}
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TEST_SOURCES ${TEST_SOURCES}
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)
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set(HIMBAECHEL_PEPPERCORN_PATH "" CACHE STRING
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"Path to a Project Peppercorn database")
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if (NOT HIMBAECHEL_PEPPERCORN_PATH)
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message(FATAL_ERROR "HIMBAECHEL_PEPPERCORN_PATH must be set to a Project Peppercorn checkout")
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endif()
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#set(ALL_HIMBAECHE_GATEMATE_DEVICES CCGM1A1 CCGM1A2 CCGM1A4 CCGM1A9 CCGM1A16 CCGM1A25)
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set(ALL_HIMBAECHE_GATEMATE_DEVICES CCGM1A1)
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set(HIMBAECHEL_GATEMATE_DEVICES ${ALL_HIMBAECHE_GATEMATE_DEVICES} CACHE STRING
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"Include support for these GateMate devices (available: ${ALL_HIMBAECHE_GATEMATE_DEVICES})")
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message(STATUS "Enabled Himbaechel-GateMate devices: ${HIMBAECHEL_GATEMATE_DEVICES}")
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foreach (device ${HIMBAECHEL_GATEMATE_DEVICES})
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if (NOT device IN_LIST ALL_HIMBAECHE_GATEMATE_DEVICES)
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message(FATAL_ERROR "Device ${device} is not a supported GateMate device")
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endif()
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add_bba_produce_command(
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TARGET nextpnr-himbaechel-gatemate-bba
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COMMAND ${Python3_EXECUTABLE}
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${CMAKE_CURRENT_SOURCE_DIR}/gen/arch_gen.py
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--lib ${HIMBAECHEL_PEPPERCORN_PATH}/gatemate
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--device ${device}
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--bba ${CMAKE_CURRENT_BINARY_DIR}/chipdb-${device}.bba.new
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OUTPUT
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${CMAKE_CURRENT_BINARY_DIR}/chipdb-${device}.bba
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INPUTS
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${CMAKE_CURRENT_SOURCE_DIR}/gen/arch_gen.py
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${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
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${CMAKE_CURRENT_SOURCE_DIR}/gfxids.inc
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)
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add_bba_compile_command(
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TARGET nextpnr-himbaechel-gatemate-chipdb
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OUTPUT himbaechel/gatemate/chipdb-${device}.bin
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INPUT ${CMAKE_CURRENT_BINARY_DIR}/chipdb-${device}.bba
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MODE binary
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)
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endforeach()
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