mirror of
https://github.com/YosysHQ/nextpnr.git
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d6483adb4d
* Initial code for GateMate * Initial work on forming bitstream * Add CCF parsing * Use CCF to set IO location * Propagate errors * Restructure code * Add support for reading from config * Start adding infrastructure for reading bitstream * Fix script * GPIO initial work * Add IN1->RAM_O2 propagation * Fixed typo * Cleanup * More parameter checks * Add LVDS support * Cleanup * Keep just used connections for now * Naive lut tree CPE pack * Naive pack CC_DFF * pack DFF fixes * Handle MUX flags * Fix DFF pack * Prevent pass trough issues * Cleanup * Use device wrapper class * Update due to API changes * Use pin connection aliases * Start work on BUFG support * Fix CC_L2T5 pack * Add CPE input inverters * Constrain routes to have correct inversion state * Add clock inversion pip * Added MX2 and MX4 support * Fix script * BUFG support * debug print if route found with wrong polarity * Some CC_DFF improvements * Create reproducible chip database * Simplify inversion of special signals * Few more DFF features * Add forgotten virtual port renames * Handle muxes with constant inputs * Allow inversion for muxes * cleanup * DFF input can be constant * init DFF only when needed * cleanup * Add basic PLL support * Add some timings * Add USR_RSTN support * Display few more primitives * Use pass trough signals to validate architecture data * Use extra tile information from chip database * Updates needed for a build system changes * Implement SB_DRIVE support * Properly named configuration bits * autogenerated constids.inc * small fix * Initial code for CPE halfs * Some cleanup * make sure FFs are compatible * reverted due to db change * Merge DFF where applicable * memory allocation issue * fix * better MX2 * ram_i handling * Cleanup MX4 * Support latches * compare L_D flag as well * Move virtual pips * Naive addf pack * carry chains grouping * Keep chip database reproducible * split addf vectors * Block CPEs when GPIO is used * Prepare placement code * RAM_I/RAM_O rewrite * fix ram_i/o index * Display RAM and add new primitives * PLL wip code * CC_PLL_ADV packing * PLL handling cleanup * Add PLL comments * Keep only high fan-out BUFG * Add skeleton for tests * Utilize move_ram_o * GPIO wip * GPIO wip * PLL fixes * cleanup * FF_OBF support * Handle FF_IBF * Make SLEW FAST if not defined as in latest p_r * Make sure FF_OBF only driving GPIO * Moved pll calc into separate file * IDDR handling and started ODDR * Route DDR input for CC_ODDR * Notify error in case ODDR or IDDR are used but not with I/O pin * cleanup for CC_USR_RSTN * Extract proper RAM location for bitstream * Code cleanup * Allow auto place of pads * Use clock source flag * Configure GPIO clock signals * Handle conflicting clk * Use BUGF in proper order * Connected CLK, works without but good for debugging * CC_CFG_CTRL placement * Group RAM data 40 bytes per row * Write BRAM content * RAM wip * Use relative constraints from chipdb * fix broken build * Memory wip * Handle custom clock for memories * Support FIFO * optimize move_ram_io * Fix SR signal handling acorrding to findings * set placer beta * Pre place what we can * Revert "debug print if route found with wrong polarity" This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe. * Revert "Constrain routes to have correct inversion state" This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803. * Remove virtual pips * Implement post processing inversion * ADDF add ability to route additional CO * Merge two ADDFs in one CPE * Added TODO * clangformat * Cleanup * Add serdes handling in config file * Cleanup * Cleanup * Cleanup * Fix in PLL handling * Fixed ADDF edge case * No need for this * Fix latch * Sanity checks * Support CC_BRAM_20K merge * Start creating testing environment * LVDS fixes * Add connection helper * Cleanup * Fix tabs * Formatting fix * Remove optimization tests for now * remove read_bitstream * removed .c_str() * Removed config parsing * using snake_case * Use bool_or_default where applicable * refactored bitstream write code * Add allow-unconstrained option * Update DFF related messages * Add clock constraint propagation --------- Co-authored-by: Lofty <dan.ravensloft@gmail.com>
98 lines
3.4 KiB
C++
98 lines
3.4 KiB
C++
/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2024 The Project Peppercorn Authors.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef HIMBAECHEL_GATEMATE_H
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#define HIMBAECHEL_GATEMATE_H
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#include "extra_data.h"
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#include "himbaechel_api.h"
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#include "log.h"
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#include "nextpnr.h"
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#include "util.h"
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#include "himbaechel_helpers.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct GateMateImpl : HimbaechelAPI
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{
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~GateMateImpl();
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void init_database(Arch *arch) override;
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void init(Context *ctx) override;
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void pack() override;
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void prePlace() override;
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void postPlace() override;
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void postRoute() override;
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bool isBelLocationValid(BelId bel, bool explain_invalid = false) const override;
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delay_t estimateDelay(WireId src, WireId dst) const override;
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void drawBel(std::vector<GraphicElement> &g, GraphicElement::style_t style, IdString bel_type, Loc loc) override;
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bool getClusterPlacement(ClusterId cluster, BelId root_bel,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const override;
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IdString getBelBucketForCellType(IdString cell_type) const override;
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
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BelBucketId getBelBucketForBel(BelId bel) const override;
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Loc getRelativeConstraint(Loc &root_loc, IdString id) const;
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void configurePlacerHeap(PlacerHeapCfg &cfg) override;
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bool isPipInverting(PipId pip) const override;
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std::set<IdString> available_pads;
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std::map<BelId, const PadInfoPOD *> bel_to_pad;
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private:
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bool getChildPlacement(const BaseClusterInfo *cluster, Loc root_loc,
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std::vector<std::pair<CellInfo *, BelId>> &placement) const;
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void write_bitstream(const std::string &device, const std::string &filename);
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void parse_ccf(const std::string &filename);
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void assign_cell_info();
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bool need_inversion(CellInfo *cell, IdString port);
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void update_cpe_lt(CellInfo *cell, IdString port, IdString init);
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void update_cpe_inv(CellInfo *cell, IdString port, IdString param);
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void update_cpe_mux(CellInfo *cell, IdString port, IdString param, int bit);
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void rename_param(CellInfo *cell, IdString name, IdString new_name, int width);
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const GateMateBelExtraDataPOD *bel_extra_data(BelId bel) const;
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struct GateMateCellInfo
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{
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// slice info
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const NetInfo *ff_en = nullptr, *ff_clk = nullptr, *ff_sr = nullptr;
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int ff_config = 0;
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int signal_used = -1;
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bool dff_used = false;
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};
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std::vector<GateMateCellInfo> fast_cell_info;
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std::map<BelId, std::map<IdString, const GateMateBelPinConstraintPOD *>> pin_to_constr;
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};
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NEXTPNR_NAMESPACE_END
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#endif
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