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mirror of https://github.com/YosysHQ/nextpnr.git synced 2026-01-11 23:53:21 +00:00
Miodrag Milanović d6483adb4d
Gatemate FPGA initial support (#1473)
* Initial code for GateMate

* Initial work on forming bitstream

* Add CCF parsing

* Use CCF to set IO location

* Propagate errors

* Restructure code

* Add support for reading from config

* Start adding infrastructure for reading bitstream

* Fix script

* GPIO initial work

* Add IN1->RAM_O2 propagation

* Fixed typo

* Cleanup

* More parameter checks

* Add LVDS support

* Cleanup

* Keep just used connections for now

* Naive lut tree CPE pack

* Naive pack CC_DFF

* pack DFF fixes

* Handle MUX flags

* Fix DFF pack

* Prevent pass trough issues

* Cleanup

* Use device wrapper class

* Update due to API changes

* Use pin  connection aliases

* Start work on BUFG support

* Fix CC_L2T5 pack

* Add CPE input inverters

* Constrain routes to have correct inversion state

* Add clock inversion pip

* Added MX2 and MX4 support

* Fix script

* BUFG support

* debug print if route found with wrong polarity

* Some CC_DFF improvements

* Create reproducible chip database

* Simplify inversion of special signals

* Few more DFF features

* Add forgotten virtual port renames

* Handle muxes with constant inputs

* Allow inversion for muxes

* cleanup

* DFF input can be constant

* init DFF only when needed

* cleanup

* Add basic PLL support

* Add some timings

* Add USR_RSTN support

* Display few more primitives

* Use pass trough signals to validate architecture data

* Use extra tile information from chip database

* Updates needed for a build system changes

* Implement SB_DRIVE support

* Properly named configuration bits

* autogenerated constids.inc

* small fix

* Initial code for CPE halfs

* Some cleanup

* make sure FFs are compatible

* reverted due to db change

* Merge DFF where applicable

* memory allocation issue

* fix

* better MX2

* ram_i handling

* Cleanup MX4

* Support latches

* compare L_D flag as well

* Move virtual pips

* Naive addf pack

* carry chains grouping

* Keep chip database reproducible

* split addf vectors

* Block CPEs when GPIO is used

* Prepare placement code

* RAM_I/RAM_O rewrite

* fix ram_i/o index

* Display RAM and add new primitives

* PLL wip code

* CC_PLL_ADV packing

* PLL handling cleanup

* Add PLL comments

* Keep only high fan-out BUFG

* Add skeleton for tests

* Utilize move_ram_o

* GPIO wip

* GPIO wip

* PLL fixes

* cleanup

* FF_OBF support

* Handle FF_IBF

* Make SLEW FAST if not defined as in latest p_r

* Make sure FF_OBF only driving GPIO

* Moved pll calc into separate file

* IDDR handling and started ODDR

* Route DDR input for CC_ODDR

* Notify error in case ODDR or IDDR are used but not with I/O pin

* cleanup for CC_USR_RSTN

* Extract proper RAM location  for bitstream

* Code cleanup

* Allow auto place of pads

* Use clock source flag

* Configure GPIO clock signals

* Handle conflicting clk

* Use BUGF in proper order

* Connected CLK, works without but good for debugging

* CC_CFG_CTRL placement

* Group RAM data 40 bytes per row

* Write BRAM content

* RAM wip

* Use relative constraints from chipdb

* fix broken build

* Memory wip

* Handle custom clock for memories

* Support FIFO

* optimize move_ram_io

* Fix SR signal handling acorrding to findings

* set placer beta

* Pre place what we can

* Revert "debug print if route found with wrong polarity"

This reverts commit cf9ded2f183db0f4e85da454e5d9f2a4da3f5cfe.

* Revert "Constrain routes to have correct inversion state"

This reverts commit 795c284d4856ff17e37d64f013775e86f1bed803.

* Remove virtual pips

* Implement post processing inversion

* ADDF add ability to route additional CO

* Merge two ADDFs in one CPE

* Added TODO

* clangformat

* Cleanup

* Add serdes handling in config file

* Cleanup

* Cleanup

* Cleanup

* Fix in PLL handling

* Fixed ADDF edge case

* No need for this

* Fix latch

* Sanity checks

* Support CC_BRAM_20K merge

* Start creating testing environment

* LVDS fixes

* Add connection helper

* Cleanup

* Fix tabs

* Formatting fix

* Remove optimization tests for now

* remove read_bitstream

* removed .c_str()

* Removed config parsing

* using snake_case

* Use bool_or_default where applicable

* refactored bitstream write code

* Add allow-unconstrained option

* Update DFF related messages

* Add clock constraint propagation

---------

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
2025-04-22 16:41:01 +02:00

85 lines
2.5 KiB
C++

/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2024 The Project Peppercorn Authors.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef GATEMATE_UTIL_H
#define GATEMATE_UTIL_H
#include <map>
#include <set>
#include <string>
#include "nextpnr.h"
#include "log.h"
NEXTPNR_NAMESPACE_BEGIN
template <typename KeyType>
double double_or_default(const dict<KeyType, Property> &ct, const KeyType &key, double def = 0)
{
auto found = ct.find(key);
if (found == ct.end())
return def;
else {
if (found->second.is_string) {
try {
return std::stod(found->second.as_string());
} catch (std::invalid_argument &e) {
log_error("Expecting numeric value but got '%s'.\n", found->second.as_string().c_str());
}
} else
return double(found->second.as_int64());
}
};
template <typename KeyType>
int extract_bits(const dict<KeyType, Property> &ct, const KeyType &key, int start, int bits, int def = 0)
{
Property extr = get_or_default(ct, key, Property()).extract(start, bits);
if (extr.is_string) {
try {
return std::stoi(extr.as_string());
} catch (std::invalid_argument &e) {
log_error("Expecting numeric value but got '%s'.\n", extr.as_string().c_str());
}
} else
return extr.as_int64();
}
template <typename T>
std::vector<std::vector<T>> splitNestedVector(const std::vector<std::vector<T>> &input, size_t maxSize = 8)
{
std::vector<std::vector<T>> result;
for (const auto &inner : input) {
size_t i = 0;
while (i < inner.size()) {
size_t end = std::min(i + maxSize, inner.size());
result.emplace_back(inner.begin() + i, inner.begin() + end);
i = end;
}
}
return result;
}
NEXTPNR_NAMESPACE_END
#endif