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YosysHQ.nextpnr/fpga_interchange/examples/remap_xilinx.v
2021-04-30 14:15:37 +01:00

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Verilog

module INV(input I, output O);
LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
endmodule
module BUF(input I, output O);
LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
endmodule