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YosysHQ.nextpnr/fpga_interchange/examples/tests/ram/run.tcl
2021-03-25 17:14:53 -07:00

18 lines
330 B
Tcl

yosys -import
foreach src $::env(SOURCES) {
read_verilog $src
}
synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp
techmap -map $::env(TECHMAP)
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json $::env(OUT_JSON)