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YosysHQ.nextpnr/fpga_interchange/examples/tests/wire/arty100t.xdc
Alessandro Comodi 15e945aa1c interchange: added boards and group testing across multiple boards 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-23 21:05:58 +01:00

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set_property PACKAGE_PIN A8 [get_ports i]
set_property PACKAGE_PIN H5 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]
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