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YosysHQ.nextpnr/fpga_interchange/examples/remap_nexus.v
2021-04-30 14:15:37 +01:00

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Verilog

// Inverter support is still a TODO
module INV(input A, output Z);
LUT4 #(.INIT("0x5555")) _TECHMAP_REPLACE_ (.A(A), .B(1'b1), .C(1'b1), .D(1'b1), .Z(Z));
endmodule