bram $__TRELLIS_DPR16X4
  init 1
  abits 4
  dbits 4
  groups 2
  ports  1 1
  wrmode 0 1
  enable 0 1
  transp 0 0
  clocks 0 1
  clkpol 0 2
endbram

# The syn_* attributes are described in:
# https://www.latticesemi.com/view_document?document_id=51556
attr_icase 1

match $__TRELLIS_DPR16X4
	attribute !syn_ramstyle syn_ramstyle=auto syn_ramstyle=distributed
	attribute !syn_romstyle syn_romstyle=auto
	attribute !ram_block
	attribute !rom_block
	attribute !logic_block
  make_outreg
  min wports 1
endmatch
