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Code Issues Releases Wiki Activity

Refactoring: Renamed RTLIL::Design::modules to modules_

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This commit is contained in:
Clifford Wolf
2014-07-27 10:18:00 +02:00
parent d088854b47
commit 10e5791c5e
73 changed files with 223 additions and 223 deletions
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14
kernel/celltypes.h
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@@ -171,7 +171,7 @@ struct CellTypes
if (cell_types.count(type) > 0)
return true;
for (auto design : designs)
if (design->modules.count(type) > 0)
if (design->modules_.count(type) > 0)
return true;
return false;
}
@@ -180,9 +180,9 @@ struct CellTypes
{
if (cell_types.count(type) == 0) {
for (auto design : designs)
if (design->modules.count(type) > 0) {
if (design->modules.at(type)->wires_.count(port))
return design->modules.at(type)->wires_.at(port)->port_output;
if (design->modules_.count(type) > 0) {
if (design->modules_.at(type)->wires_.count(port))
return design->modules_.at(type)->wires_.at(port)->port_output;
return false;
}
return false;
@@ -203,9 +203,9 @@ struct CellTypes
{
if (cell_types.count(type) == 0) {
for (auto design : designs)
if (design->modules.count(type) > 0) {
if (design->modules.at(type)->wires_.count(port))
return design->modules.at(type)->wires_.at(port)->port_input;
if (design->modules_.count(type) > 0) {
if (design->modules_.at(type)->wires_.count(port))
return design->modules_.at(type)->wires_.at(port)->port_input;
return false;
}
return false;