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Fix FIRRTL to Verilog process instance subfield assignment.

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Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
This commit is contained in:
Jim Lawson
2019-02-25 16:18:13 -08:00
parent c258b99040
commit 171c425cf9
4 changed files with 21 additions and 11 deletions
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tests/simple/xfirrtl
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@@ -12,7 +12,6 @@ multiplier.v inst id[0] of
muxtree.v drops modules
omsp_dbg_uart.v $adff
operators.v $pow
paramods.v subfield assignment (bits() <= ...)
partsel.v drops modules
process.v drops modules
realexpr.v drops modules