Added support for SystemVerilog packages with localparam definitions
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@@ -18,6 +18,7 @@
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*/
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#include "kernel/yosys.h"
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#include "frontends/ast/ast.h"
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#ifndef RTLIL_H
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#define RTLIL_H
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@@ -792,6 +793,7 @@ struct RTLIL::Design
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int refcount_modules_;
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dict<RTLIL::IdString, RTLIL::Module*> modules_;
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std::vector<AST::AstNode*> packages;
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std::vector<RTLIL::Selection> selection_stack;
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dict<RTLIL::IdString, RTLIL::Selection> selection_vars;
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