Merge pull request #5192 from garytwong/multiline-string

verilog: support newline and hex escapes in string literals

docs/source/yosys_internals/verilog.rst

@@ -381,3 +381,6 @@ from SystemVerilog:
   will process conditionals using these keywords by annotating their
   representation with the appropriate ``full_case`` and/or ``parallel_case``
   attributes, which are described above.)
+
+- SystemVerilog string literals are supported (triple-quoted strings and
+  escape sequences such as line continuations and hex escapes).