Make liberal use of IdString.in()
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@@ -262,7 +262,7 @@ struct MemoryDffWorker
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mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
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mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
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}
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if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
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if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
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SigSpec sig_a = cell->getPort("\\A");
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SigSpec sig_y = cell->getPort("\\Y");
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if (cell->type == "$not")
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@@ -155,7 +155,7 @@ struct MemoryShareWorker
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{
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bool ignore_data_port = false;
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if (cell->type == "$mux" || cell->type == "$pmux")
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if (cell->type.in("$mux", "$pmux"))
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{
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std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
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std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
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@@ -173,7 +173,7 @@ struct MemoryShareWorker
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continue;
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}
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if ((cell->type == "$memwr" || cell->type == "$memrd") &&
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if (cell->type.in("$memwr", "$memrd") &&
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cell->parameters.at("\\MEMID").decode_string() == memid)
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ignore_data_port = true;
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@@ -690,7 +690,7 @@ struct MemoryShareWorker
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sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
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}
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if (cell->type == "$mux" || cell->type == "$pmux")
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if (cell->type.in("$mux", "$pmux"))
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{
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std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
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for (int i = 0; i < int(sig_y.size()); i++)
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