github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-25 20:06:27 +00:00
Code Issues Releases Wiki Activity

docs: Remove TODOs from output

Browse Source 
Remove highlighting of wreduce/opt_clean bug.
This commit is contained in:
Krystine Sherwin
2024-03-05 05:44:40 +13:00
parent 9eed04dd4b
commit 3596025283
4 changed files with 4 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
docs/source/code_examples/fifo/fifo.out
View File

@@ -357,9 +357,7 @@ Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$f
Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:68$27_Y.
Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:20$34_Y.
yosys> select -set new_cells t:$add %co t:$add %d
yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
20. Generating Graphviz representation of design.
Writing dot description to `rdata_wreduce.dot'.

3
docs/source/code_examples/fifo/fifo.ys
View File

@@ -53,8 +53,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata
# ========================================================
wreduce
select -set new_cells t:$add %co t:$add %d
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
show -notitle -format dot -prefix rdata_wreduce o:rdata %ci*
# unclear if this is necessary or only because of bug(s)
opt_clean