Add $cover cell type and SVA cover() support

techlibs/common/simlib.v

@@ -1305,6 +1305,14 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$cover (A, EN);
+
+input A, EN;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$initstate (Y);
 
 output reg Y = 1;