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Docs: Apply invert-helper where needed

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Krystine Sherwin
2024-05-11 10:40:54 +12:00
parent 9be7089f4f
commit 3a36612ec7
17 changed files with 93 additions and 93 deletions
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docs/source/appendix/primer.rst
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@@ -24,7 +24,7 @@ circuit to a functionally equivalent low-level representation of a circuit.
abstraction and how they relate to different kinds of synthesis.
.. figure:: /_images/primer/basics_abstractions.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Basics_abstractions
Different levels of abstraction and synthesis.
@@ -499,7 +499,7 @@ using a series of tools and the results are again verified using simulation.
This process is illustrated in :numref:`Fig. %s <fig:Basics_flow>`.
.. figure:: /_images/primer/basics_flow.*
:class: width-helper
:class: width-helper invert-helper
:name: fig:Basics_flow
Typical design flow. Green boxes represent manually created models.
@@ -598,7 +598,7 @@ Let's consider the following BNF (in Bison syntax):
expr: TOK_IDENTIFIER | TOK_NUMBER | expr TOK_PLUS expr;
.. figure:: /_images/primer/basics_parsetree.*
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:class: width-helper invert-helper
:name: fig:Basics_parsetree
Example parse tree for the Verilog expression
@@ -627,7 +627,7 @@ suitable for further processing. In compilers this is often an assembler-like
three-address-code intermediate representation. :cite:p:`Dragonbook`
.. figure:: /_images/primer/basics_ast.*
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:class: width-helper invert-helper
:name: fig:Basics_ast
Example abstract syntax tree for the Verilog expression