xilinx: add delays to INV

2026-04-25 03:46:21 +00:00 · 2020-02-18 11:03:38 -08:00
parent 6bb3d9f9c0
commit 3b74e0fa45
1 changed files with 3 additions and 0 deletions
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -160,6 +160,9 @@ module INV(
    input I
 );
  assign O = !I;
+  specify
+    (I => O) = 127;
+  endspecify
 endmodule

 (* abc9_lut=1 *)