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Merge pull request #2006 from jersey99/signed-in-rtlil-wire

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Preserve 'signed'-ness of a verilog wire through RTLIL
This commit is contained in:
whitequark
2020-06-04 11:23:06 +00:00
committed by GitHub
parent 44f1e65155 adb483ddfd
commit 3bffd09d64
7 changed files with 19 additions and 2 deletions
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1
frontends/ast/genrtlil.cc
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@@ -1065,6 +1065,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
wire->is_signed = is_signed;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)

3
frontends/ilang/ilang_parser.y
View File

@@ -192,6 +192,9 @@ wire_options:
wire_options TOK_UPTO {
current_wire->upto = true;
} |
wire_options TOK_SIGNED {
current_wire->is_signed = true;
} |
wire_options TOK_OFFSET TOK_INT {
current_wire->start_offset = $3;
} |

7
frontends/json/jsonparse.cc
View File

@@ -309,6 +309,12 @@ void json_import(Design *design, string &modname, JsonNode *node)
port_wire->upto = val->data_number != 0;
}
if (port_node->data_dict.count("signed") != 0) {
JsonNode *val = port_node->data_dict.at("signed");
if (val->type == 'N')
port_wire->is_signed = val->data_number != 0;
}
if (port_node->data_dict.count("offset") != 0) {
JsonNode *val = port_node->data_dict.at("offset");
if (val->type == 'N')
@@ -573,4 +579,3 @@ struct JsonFrontend : public Frontend {
} JsonFrontend;
YOSYS_NAMESPACE_END