Added read_verilog -sv options, added support for bit, logic,

allways_ff, always_comb, and always_latch

tests/sat/asserts.ys

@@ -1,3 +1,3 @@
-read_verilog asserts.v
+read_verilog -sv asserts.v
 hierarchy; proc; opt
 sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts

tests/sat/asserts_seq.ys

@@ -1,4 +1,4 @@
-read_verilog asserts_seq.v
+read_verilog -sv asserts_seq.v
 hierarchy; proc; opt
 
 sat -verify  -prove-asserts -tempinduct -seq 1 test_001