From 4ac100fe137e79baf50363e94aa088854c21838f Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Wed, 6 Aug 2025 18:11:05 +1200
Subject: [PATCH] cutpoint: Track wire drivers

Necessary to avoid multiple drivers being inserted when a blackbox has inout ports (like when importing an unknown module with `verific`).
If any bits of an inout port have a known driver, treat the port as an input.
If there are no bits with a known driver, treat the port as an output, and mark each bit as having a driver.
---
 passes/sat/cutpoint.cc | 34 ++++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index 485e44fd6..41fa9fac4 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -109,13 +109,43 @@ struct CutpointPass : public Pass {
 			SigMap sigmap(module);
 			pool<SigBit> cutpoint_bits;
 
+			pool<SigBit> wire_drivers;
+			for (auto cell : module->cells())
+				for (auto &conn : cell->connections())
+					if (cell->output(conn.first) && !cell->input(conn.first))
+						for (auto bit : sigmap(conn.second))
+							if (bit.wire)
+								wire_drivers.insert(bit);
+			
+			for (auto wire : module->wires())
+				if (wire->port_input)
+					for (auto bit : sigmap(wire))
+						wire_drivers.insert(bit);
+
 			for (auto cell : module->selected_cells()) {
 				if (cell->type == ID($anyseq))
 					continue;
 				log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
 				for (auto &conn : cell->connections()) {
-					if (cell->output(conn.first))
-						module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
+					if (cell->output(conn.first)) {
+						bool do_cut = true;
+						if (cell->input(conn.first))
+							for (auto bit : sigmap(conn.second))
+								if (wire_drivers.count(bit)) {
+									log_debug("  Treating inout port '%s' as input.\n", id2cstr(conn.first));
+									do_cut = false;
+									break;
+								}
+
+						if (do_cut) {
+							module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
+							if (cell->input(conn.first)) {
+								log_debug("  Treating inout port '%s' as output.\n", id2cstr(conn.first));
+								for (auto bit : sigmap(conn.second))
+									wire_drivers.insert(bit);
+							}
+						}
+					}
 				}
 
 				RTLIL::Cell *scopeinfo = nullptr;