1
0
mirror of synced 2026-04-26 12:18:43 +00:00

Refactoring: Renamed RTLIL::Module::cells to cells_

This commit is contained in:
Clifford Wolf
2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions

View File

@@ -40,7 +40,7 @@ struct ConstEval
ct.setup_internals();
ct.setup_stdcells();
for (auto &it : module->cells) {
for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
continue;
for (auto &it2 : it.second->connections())