github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 15:45:07 +00:00
Code Issues Releases Wiki Activity

Refactoring: Renamed RTLIL::Module::cells to cells_

Browse Source
This commit is contained in:
Clifford Wolf
2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/simplemap.cc
View File

@@ -439,7 +439,7 @@ struct SimplemapPass : public Pass {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> delete_cells;
for (auto &cell_it : mod_it.second->cells) {
for (auto &cell_it : mod_it.second->cells_) {
if (mappers.count(cell_it.second->type) == 0)
continue;
if (!design->selected(mod_it.second, cell_it.second))