verilog: add support for SystemVerilog string literals.

Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.

docs/source/using_yosys/verilog.rst

@@ -379,3 +379,6 @@ from SystemVerilog:
   will process conditionals using these keywords by annotating their
   representation with the appropriate ``full_case`` and/or ``parallel_case``
   attributes, which are described above.)
+
+- SystemVerilog string literals are supported (triple-quoted strings and
+  escape sequences such as line continuations and hex escapes).