Fixes in $alu SAT- and eval-models
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@@ -178,8 +178,8 @@ struct ConstEval
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RTLIL::SigSpec sig_co = cell->getPort("\\CO");
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bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
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sig_a.extend(SIZE(sig_y), signed_a);
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sig_b.extend(SIZE(sig_y), signed_b);
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sig_a.extend_u0(SIZE(sig_y), signed_a);
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sig_b.extend_u0(SIZE(sig_y), signed_b);
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bool carry = sig_ci[0] == RTLIL::S1;
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bool b_inv = sig_bi[0] == RTLIL::S1;
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