Added more generic _TECHMAP_ wire mechanism to techmap pass

2026-04-30 21:50:07 +00:00 · 2013-11-23 15:58:06 +01:00
parent 9ab850e45e
commit 532091afcb
3 changed files with 193 additions and 79 deletions
--- a/techlibs/xilinx/cells.v
+++ b/techlibs/xilinx/cells.v
@@ -46,7 +46,7 @@ module \$lut (I, O);
        .I0(I[0]), .I1(I[1]), .I2(I[2]),
        .I3(I[3]), .I4(I[4]), .I5(I[5]));
    end else begin:error
-      wire TECHMAP_FAIL;
+      wire _TECHMAP_FAIL_ = 1;
    end
  endgenerate