diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 1c0e16735..fcdbab555 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -3259,16 +3259,10 @@ endmodule
 //- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
 //-
 module \$priority (A, Y);
-	parameter WIDTH = 0;
-	parameter P_WIDTH = 0;
-	parameter POLARITY = 0;
-	input  [P_WIDTH*WIDTH-1:0] A;
-	output [P_WIDTH*WIDTH-1:0] Y;
+parameter WIDTH = 8;
+input  [WIDTH-1:0] A;
+output [WIDTH-1:0] Y;
+
+assign Y = A & (~A + 1);
 
-	genvar offset;
-	generate
-		for (offset = 0; offset < P_WIDTH*WIDTH; offset = offset + P_WIDTH) begin
-			assign Y[offset : offset+P_WIDTH-1] = POLARITY[offset : offset+P_WIDTH-1] ^ ((A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) & (~(A[offset : offset+P_WIDTH-1] ^ POLARITY[offset : offset+P_WIDTH-1]) + 1));
-		end
-	endgenerate
 endmodule