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Fix debug

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This commit is contained in:
Eddie Hung
2019-11-25 12:59:34 -08:00
parent d087024caf
commit 6831510f5b
1 changed files with 3 additions and 3 deletions
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6
passes/techmap/abc9.cc
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@@ -347,10 +347,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
log_assert(!design->module(ID($__abc9__)));
{
AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
reader.parse_xaiger();
reader.parse_xaiger(box_lookup);
}
ifs.close();
Pass::call(design, stringf("write_verilog -noexpr -norename"));
Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
design->remove(design->module(ID($__abc9__)));
#endif
@@ -421,7 +421,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
ifs.close();
#if 0
Pass::call(design, stringf("write_verilog -noexpr -norename"));
Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
#endif
log_header(design, "Re-integrating ABC9 results.\n");