Reject wide ports in some passes that will never support them.
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@@ -1057,6 +1057,20 @@ void handle_memory(Mem &mem, const rules_t &rules)
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log(" %s=%d", it.first.c_str(), it.second);
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log("\n");
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for (auto &port : mem.rd_ports) {
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if (port.wide_log2) {
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log("Wide read ports are not supported, skipping.\n");
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return;
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}
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}
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for (auto &port : mem.wr_ports) {
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if (port.wide_log2) {
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log("Wide write ports are not supported, skipping.\n");
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return;
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}
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}
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pool<pair<IdString, int>> failed_brams;
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dict<pair<int, int>, tuple<int, int, int>> best_rule_cache;
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