From 69ff2fb4846d9900b9527dddbaedb6531cd00f99 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 7 Apr 2026 20:05:51 +0200 Subject: [PATCH] rtlil: sigNormalize Module when added to Design in signorm mode --- kernel/rtlil.cc | 16 ---------------- kernel/rtlil_bufnorm.cc | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f019025d0..e8f713c24 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1215,22 +1215,6 @@ RTLIL::Module *RTLIL::Design::top_module() const return module_count == 1 ? module : nullptr; } -void RTLIL::Design::add(RTLIL::Module *module) -{ - log_assert(modules_.count(module->name) == 0); - log_assert(refcount_modules_ == 0); - modules_[module->name] = module; - module->design = this; - - for (auto mon : monitors) - mon->notify_module_add(module); - - if (yosys_xtrace) { - log("#X# New Module: %s\n", log_id(module)); - log_backtrace("-X- ", yosys_xtrace-1); - } -} - void RTLIL::Design::add(RTLIL::Binding *binding) { log_assert(binding != nullptr); diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index 64943a01a..b65cfdc61 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -1204,4 +1204,25 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) } +void RTLIL::Design::add(RTLIL::Module *module) +{ + log_assert(modules_.count(module->name) == 0); + log_assert(refcount_modules_ == 0); + modules_[module->name] = module; + module->design = this; + + for (auto mon : monitors) + mon->notify_module_add(module); + + if (yosys_xtrace) { + log("#X# New Module: %s\n", log_id(module)); + log_backtrace("-X- ", yosys_xtrace-1); + } + + if (flagSigNormalized) { + module->sigNormalize(); + } + +} + YOSYS_NAMESPACE_END