Update test with a/b reset
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@@ -61,10 +61,12 @@ always @(posedge clk) begin
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// Store accumulation result into a register
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adder_out <= adder_out + mult_reg;
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end
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if (rst) begin
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if (rst) begin
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a_reg <= 0;
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b_reg <= 0;
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mult_reg <= 0;
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adder_out <= 0;
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end
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end
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end
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// Output accumulation result
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