Another block of spelling fixes

Smaller this time

techlibs/common/techmap.v

@@ -19,7 +19,7 @@
  *
  *  The internal logic cell technology mapper.
  *
- *  This verilog library contains the mapping of internal cells (e.g. $not with
+ *  This Verilog library contains the mapping of internal cells (e.g. $not with
  *  variable bit width) to the internal logic cells (such as the single bit $_NOT_
  *  gate). Usually this logic network is then mapped to the actual technology
  *  using e.g. the "abc" pass.